I've been working my way through the nand2tetris book, and am at the point where you pull everything together into a working computer. I got distracted and haven't had the chance to come back to it. But I had plans… Once I'd finished the CPU design I was going to implement it in Verilog for the DE10 nano . The idea was to output the design's screen to a texture that Linux running on the ARM SoC could put into a window. I'd actually started on the Verilog for different components of the system, although that was just to complete the lessons, using someone else's Verilog of the different chips as a base, and improved on their designs. They were using too many gates for their adder, I believe, among other inefficiencies. I'm a neophyte at FPGA design, but I realized that implementing all the multiplexers and RAM using NAND gates directly was going to under-perform. Not that the design needs the full 50 MHz offered by the board, but it's the principle of t...